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ADS1203
SBAS318 - JUNE 2004
Motor Control Current Measurement 1 Bit, 10MHz, 2nd Order, Delta Sigma Modulator
FEATURES D 16-Bit Resolution D 14-Bit Linearity D 250mV Input Range with Single +5V Supply D 1% Internal Reference Voltage D 1% Gain Error D Flexible Serial Interface with Four Different
Modes
DESCRIPTION
The ADS1203 is a delta-sigma () modulator with a 95dB dynamic range, operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers or low-level signals. With the appropriate digital filter and modulator rate, the device can be used to achieve 16-bit analog-to-digital (A/D) conversion with no missing codes. An effective resolution of 14 bits or SNR of 85dB (typical) can be maintained with a digital filter bandwidth of 40kHz at a modulator rate of 10MHz. The ADS1203 is designed for use in medium- to high-resolution measurement applications including current measurements, smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. It is available in an 8-lead TSSOP package. A 16-pin QFN (3x3) package will be available soon.
D Implemented Twinned Binary Coding as D
Split-Phase or Manchester Coding for One-Line Interfacing Operating Temperature Range: -40C to +85C
APPLICATIONS D Motor Control D Current Measurement D Industrial Process Control D Instrumentation D Smart Transmitters D Portable Instruments D Weight Scales D Pressure Transducers
VIN+ VIN-
2nd-Order Modulator
MDAT MCLK
VDD GND Buffer
RC Oscillator 20MHz
Interface Circuit M0 M1
Reference Voltage 2.5V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
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ADS1203
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) 3 MAXIMUM GAIN ERROR (%) PACKAGELEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY
ADS1203(2)
1
ADS1203IPWT TSSOP-8 PW -40C to +85C AZ1203 ADS1203IPWR
Tape and Reel, 250 Tape and Reel, 2000
(1) For the most current specification and package information, refer to our web site at www.ti.com. (2) 16-pin QFN (3x3) package available soon.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) ADS1203 Supply voltage, GND to VDD Analog input voltage range Digital input voltage range Power Dissipation Operating Virtual Junction Temperature Range, TJ Operating Free-Air Temperature Range, TA Storage Temperature Range, TSTG -0.3 to +6 GND - 0.4 to VDD + 0.3 GND - 0.3 to VDD + 0.3 0.25 -40 to +150 -40 to +85 -65 to +150 UNIT V V V W C C C
Lead Temperature (1.6mm or 1/16 from case for 10s) +260 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage, VDD Analog Input Voltage Operating Common-Mode Signal External Clock(1) MIN 4.5 -250 0 16 20 NOM 5.0 MAX 5.5 +250 +5 24 +105 UNIT V mV V MHz C
Operating Junction Temperature Range -40 (1) With reduced accuracy, clock can go from 1MHz up to 32MHz; see Typical Characteristic curves.
DISSIPATION RATING TABLE
PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C(1) TA = 70C POWER RATING TA = 85C POWER RATING
TSSOP-8 483.6mW 3.868mW/C 309.5mW 251.4W (1) This is the inverse of the traditional junction-to-ambient thermal resistance (Rq JA). Thermal resistances are not production tested and are for informational purposes only.
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ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at -40C to +85C, VDD = +5V, VIN+ = -250mV to +250mV, VIN- = 0V, Mode 3, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. PARAMETER Resolution DC Accuracy INL DNL VOS TCVOS GERR TCGERR PSRR Integral linearity error(2) Differential nonlinearity(3) Input offset Input offset drift Gain error(4) Gain error drift Power-supply rejection ratio 4.75V < VDD < 5.25V (VIN+) - (VIN-) -0.1 Common-mode 3 1 Equivalent 28 5 At DC CMRR Common-mode rejection ratio VIN = 0V to 5V at 50kHz Scale to 320mV Scale to 320mV 20 80 to 0.1% at CL = 0 9 0.1 2.475 92 105 -220 3.5 -0.2 20 80 320 5 1 0.001 3 0.005 1 1000 8 1 LSB % LSB V V/C % ppm/C dB TEST CONDITIONS MIN 16 ADS1203IPW TYP(1) MAX UNITS Bits
Analog Input FSR Full-scale differential range Operating common-mode signal(3) Input capacitance Input leakage current Differential input resistance Differential input capacitance mV V pF nA k pF dB dB
Internal Voltage Reference VOUT dVOUT/dT PSRR Reference voltage output Accuracy Reference temperature drift Power-supply rejection ratio Startup time Internal Clock for Modes 0, 1, and 2 Clock frequency External Clock for Mode 3 Clock frequency(5) AC Accuracy SINAD SNR THD SFDR Signal-to-noise + distortion Signal-to-noise ratio Total harmonic distortion Spurious-free dynamic range VIN = 250mVPP at 5kHz VIN = 250mVPP at 5kHz VIN = 250mVPP at 5kHz VIN = 250mVPP at 5kHz 90 82.5 83 85 85 -95 95 -88 dB dB dB dB 16 20 24 MHz 10 11 MHz 2.5 2.525 1 V % ppm/C dB ms
(1) All typical values are at TA = +25C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for VIN+ = -250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) With reduced accuracy, minimum clock can go from 1MHz up to 32MHz.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at -40C to +85C, VDD = +5V, VIN+ = -250mV to +250mV, VIN- = 0V, Mode 3, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. PARAMETER Digital Input Logic family VIH VIL IIH IIL CI High-level input voltage Low-level input voltage High-level Input current Low-level Input current Input capacitance VI = VDD or GND VI = VDD or GND -50 5 CMOS with Schmitt Trigger 0.7 x VDD -0.3 VDD + 0.3 0.3xVDD 50 V V nA nA pF TEST CONDITIONS MIN ADS1203IPW TYP(1) MAX UNITS
Digital Output VOH VOL CO CL VDD ICC High-level digital output VDD = 5V, IO = -5mA VDD = 5V, IO = -15mA VDD = 5V, IO = 5mA VDD = 5V, IO = 15mA 5 30 4.6 3.9 0.4 1.1 V V V V pF pF
Low-level digital output Output capacitance Load capacitance
Power Supply Supply voltage Mode 0 Operating supply current Mode 3 Mode 0 Power dissipation Operating Temperature Range Mode 3 -40 4.5 5 8.4 6.7 42 33.5 5.5 9.8 7.8 49 39 +85 V mA mA mW mW C
(1) All typical values are at TA = +25C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for VIN+ = -250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. (5) With reduced accuracy, minimum clock can go from 1MHz up to 32MHz.
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EQUIVALENT INPUT CIRCUIT
VDD RON = 350 AIN C(SAMPLE) = 5pF DIN VDD
GND Diode Turn-on Voltage: 0.4V Equivalent Analog Input Circuit
GND
Equivalent Digital Input Circuit
PIN ASSIGNMENTS
TSSOP PACKAGE (TOP VIEW) TERMINAL NAME M0
M0 VIN+ VIN- M1 1 2 ADS1203 3 4 6 5 MDAT GND 8 7 VDD MCLK
Terminal Functions
NO. 1 2 3 4 5 6 7 8
I/O I AI AI I P O I/O P Mode input
DESCRIPTION
VIN+ VIN- M1 GND MDAT MCLK VDD
Noninverting analog input Inverting analog input Mode input Power supply ground Modulator data output Modulator clock input or output Power supply: +5V nominal
NOTE: AI = analog input, AO = analog output, I = input, O = output, P = power supply.
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PARAMETER MEASUREMENT INFORMATION
tC1 MCLK tW1 tD1
MDAT
Figure 1. Mode 0 Operation
TIMING CHARACTERISTICS: MODE 0
over recommended operating free-air temperature range at -40C to +85C, and VDD = +5V, unless otherwise noted. PARAMETER tC1 tW1 tD1 Clock period Clock high time Data delay after falling edge of clock MODE 0 0 0 MIN 91 (tC1/2) - 5 -2 MAX 111 (tC1/2) + 5 2 UNIT ns ns ns
t C2 MCLK t W2 MDAT tD2 tD3
Figure 2. Mode 1 Operation
TIMING CHARACTERISTICS: MODE 1
over recommended operating free-air temperature range at -40C to +85C, and VDD = +5V, unless otherwise noted. PARAMETER tC2 tW2 tD2 tD3 Clock period Clock high time Data delay after rising edge of clock Data delay after falling edge of clock MODE 1 1 1 1 MIN 182 (tC2/2) - 5 (tW2/2) - 2 (tW2/2) - 2 MAX 222 (tC2/2) + 5 (tW2/2) + 2 (tW2/2) + 2 UNIT ns ns ns ns
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t C1 Internal MCLK tW1 Internal MDAT tW3 tC3
MDAT 1 0 1 1 0 0
Figure 3. Mode 2 Operation
TIMING CHARACTERISTICS: MODE 2
over recommended operating free-air temperature range at -40C to +85C, and VDD = +5V, unless otherwise noted. PARAMETER tC1 tW1 tC3 tW3 Clock period Clock high time Clock period Clock high time MODE 2 2 2 2 MIN 91 (tC1/2) - 5 91 (tC3/2) - 5 MAX 111 (tC1/2) + 5 111 (tC3/2) + 5 UNIT ns ns ns ns
tC4 MCLK tW4 tD4
MDAT
Figure 4. Mode 3 Operation
TIMING CHARACTERISTICS: MODE 3
over recommended operating free-air temperature range at -40C to +85C, and VDD = +5V, unless otherwise noted. PARAMETER tC4 tW4 tD4 tR tF Clock period Clock high time Data delay after falling edge of clock Rise time of clock Fall time of clock MODE 3 3 3 3 3 MIN 41 10 0 0 0 MAX 62 tC4 - 10 10 10 10 UNIT ns ns ns ns ns
NOTE: Clock signal is specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; see Figure 4.
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TYPICAL CHARACTERISTICS
VDD = +5V, VIN+ = -250mV to +250mV, VIN- = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 0) 4 3 2 1 INL (LSB) INL (LSB) 0 -1 -2 -3 -4 -5 -320 -240 -160 -80 0 80 160 240 320 +25_C -40_C +85_C 4 3 2 1 0 -1 -2 -3 -4 -5 -320
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 3, MCLK = 20MHz)
-40_ C
+25_C
+85_C
-240
-160
-80
0
80
160
240
320
Differential Input Voltage (mV)
Differential Input Voltage (mV)
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 3, MCLK = 32MHz) 4 3
INTEGRAL NONLINEARITY vs TEMPERATURE 5 Mode 3 (MCLK = 32MHz) 4 0.0061 0.0076
2 INL (LSB) 1 INL (LSB) 0 -1 -2 -3 -4 -5 -320 -240 -160 -80 0 +85_C -40_C INL (%) 3 Mode 0 2 Mode 3 (MCLK = 20MHz) 1 +25_C 0 80 160 240 320 Differential Input Voltage (mV) -40 -20 0 100 0.0015 0.0031 0.0046
0
20
40
60
80
Temperature (_C)
OFFSET vs TEMPERATURE 0 -100 -200 Offset (V) Offset (V) -300 -400 -500 -600 -700 Mode 3 (MCLK = 32MHz) Mode 3 (MCLK = 20MHz) Mode 0 0 -100 -200 -300 -400 -500 -600 -700 -800 0 20 40 60 80 100 4.5 4.6 4.7
OFFSET vs POWER SUPPLY
Mode 3 (MCLK = 20MHz)
Mode 0
Mode 3 (MCLK = 32MHz)
-800 -40
-20
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
Temperature (_C)
Power Supply (V)
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TYPICAL CHARACTERISTICS (continued)
VDD = +5V, VIN+ = -250mV to +250mV, VIN- = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
GAIN vs TEMPERATURE 0.10 0 -0.10 Gain (%) -0.20 -0.30 -0.40 -0.50 -40 Mode 3 (MCLK = 32MHz) 2 0 -320 Mode 3 (MCLK = 20MHz) Mode 0 14 12 RMS Noise (V) 10 8 6 4
RMS NOISE vs INPUT VOLTAGE LEVEL
-20
0
20 40 Temperature (_ C)
60
80
100
-240
-160
-80
0
80
160
240
320
Differential Input Voltage (mV)
SIGNAL-TO-NOISE RATIO vs TEMPERATURE 85.6 Mode 3 (MCLK = 32MHz) 85.4 85.2 85.0 84.8 84.6 Mode 0 84.4 84.2 SINAD (dB) SNR (dB) Mode 3 (MCLK = 20MHz) 85.2 84.8 84.4 84.0 83.6 83.2 82.8 82.4 82.0 81.6 81.2 -40 -20 80.8 0 20 40 60 80 100 Temperature (_C) -40 -20
SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE Mode 3 (MCLK = 20MHz)
Mode 0
Mode 3 (MCLK = 32MHz)
0
20
40
60
80
100
Temperature (_ C)
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 18 16 ENOB (Bits) 14 12 10 8 6 4 10 100 1k 10k Decimation Ratio (OSR) Sinc3 Filter Sinc2 Filter 62 50 6 38 26 5 -40 110 98 9 86 Current (mA) 74 SNR (dB) 8 10
POWER-SUPPLY CURRENT vs TEMPERATURE
Mode 0
Mode 3 (MCLK = 32MHz) 7 Mode 3 (MCLK = 20MHz)
-20
0
20
40
60
80
100
Temperature (_C)
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TYPICAL CHARACTERISTICS (continued)
VDD = +5V, VIN+ = -250mV to +250mV, VIN- = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 0) 105 103 101 99 SFDR (dB) 97 95 93 91 89 87 85 -40 -20 0 20 40 Temperature (_C) 60 80 100 THD SFDR 0.5VPP 5kHz -105 -103 -101 -99 -95 -93 -91 -89 -87 -85 THD (dB) -97 SFDR (dB) 105 103 101 99 97 95 93 91 89 87 85 -40 -20 0 20 40 Temperature (_ C) 60 80 100 0.5VPP 5kHz THD SFDR SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 3, MCLK = 20MHz) -105 -103 -101 -99 -95 -93 -91 -89 -87 -85 THD (dB) THD (dB) THD (dB) -97
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 3, MCLK = 32MHz) 105 103 101 99 SFDR (dB) 97 95 93 91 89 87 85 -40 -20 0 20 40 Temperature (_ C) 60 80 100 0.5VPP 5kHz THD SFDR -105 -103 -101 -99 THD (dB) -97 -95 -93 -91 -89 -87 -85 50 SFDR (dB) 100 90 80 70 60 110
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 0) -110 SFDR THD -100 -90 -80 -70 -60 -50 1 Frequency (kHz) 10 20
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 3, MCLK = 20MHz) 110 100 90 SFDR (dB) 80 70 60 50 1 Frequency (kHz) 10 20 SFDR THD -110 -100 -90 -80 -70 -60 -50 THD (dB) 110
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 3, MCLK = 32MHz) -110 SFDR 100 THD 90 SFDR (dB) 80 70 60 50 1 Frequency (kHz) 10 20 -90 -80 -70 -60 -50 -100
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TYPICAL CHARACTERISTICS (continued)
VDD = +5V, VIN+ = -250mV to +250mV, VIN- = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
FREQUENCY SPECTRUM (4096 Point FFT, fIN = 1kHz, 0.5VPP) 0 -20 Magnitude (dB) Magnitude (dB) -40 -60 -80 -100 -120 -140 0 5 10 Frequency (kHz) 15 20 0 -20 -40 -60 -80 -100 -120 -140 0
FREQUENCY SPECTRUM (4096 Point FFT, fIN = 5kHz, 0.5VPP)
5
10 Frequency (kHz)
15
20
CLOCK FREQUENCY vs TEMPERATURE 10.8 10.5
CLOCK FREQUENCY vs POWER SUPPLY
10.5 MCLK (MHz) MCLK (MHz) -40 -20
10.3
10.2
10.1
9.9
9.9
9.6
9.7
9.3 0 20 40 Temperature (_ C) 60 80 100
9.5 4.5 4.7 4.9 5.1 Power Supply (V) 5.3 5.5
COMMON-MODE REJECTION RATIO vs FREQUENCY 110 105 100 95 CMRR (dB) 90 85 80 75 70 65 60 1 10 Input Frequency (kHz) 100 55 50 0.1 PSRR (dB) 80 75 70 65 60 90 85
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
1 10 Frequency of Power Supply (kHz)
100
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TYPICAL CHARACTERISTICS (continued)
VDD = +5V, VIN+ = -250mV to +250mV, VIN- = 0V, MCLK input = 20MHz, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
MCLK AND MDAT TYPICAL SINK CURRENT 70 5.5V 60 Output Current, IOH (mA) Output Current, IOL (mA) 50 5V 40 4.5V 30 20 10 0 0 1 2 3 4 5 6 Output Voltage, VOL (V) 70 60 50 40 30 80
MCLK AND MDAT TYPICAL SOURCE CURRENT
5.5V 5V
4.5V 20 10 0 0 1 2 3 4 Output Voltage, VOH (V) 5 6
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GENERAL DESCRIPTION
The ADS1203 is a single-channel, 2nd-order, CMOS delta-sigma modulator, designed for medium- to high-resolution A/D conversions from DC to 39kHz with an oversampling ratio (OSR) of 256. The output of the converter (MDAT) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage. The modulator shifts the quantization noise to high frequencies. A low-pass digital filter should be used at the output of the delta-sigma modulator. The primary purpose of the digital filter is to filter out high-frequency noise. The secondary purpose is to convert the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). A digital signal processor (DSP), microcontroller (C), or field programmable gate array (FPGA) could be used to implement the digital filter. Figure 5 shows the ADS1203 connected to a DSP. The overall performance (speed and accuracy) depends on the selection of an appropriate OSR and filter type. A higher OSR produces greater output accuracy while operating at a lower refresh rate. Alternatively, a lower OSR produces lower output accuracy, but operates at a higher refresh rate. This system allows flexibility with the digital filter design and is capable of A/D conversion results that have a dynamic range exceeding 95dB with an OSR = 256.
variety of solutions and signal bandwidths (however, this can only be used in mode 3). The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream, which accurately represents the analog input voltage over time, appears at the output of the converter.
ANALOG INPUT STAGE
Analog Input The input design topology of the ADS1203 is based on a fully differential switched-capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (92dB), and excellent power-supply rejection. The input impedance of the analog input is dependent on the modulator clock frequency (fCLK), which is also the sampling frequency of the modulator. Figure 6 shows the basic input structure of the ADS1203. The relationship between the input impedance of the ADS1203 and the modulator clock frequency is: Z IN + 28kW f CLK 10MHz (1)
THEORY OF OPERATION
The differential analog input of the ADS1203 is implemented with a switched-capacitor circuit. This circuit implements a 2nd-order modulator stage, which digitizes the analog input signal into a 1-bit output stream. The clock source can be internal as well as external. Different frequencies for this clock allow for a
The input impedance becomes a consideration in designs where the source impedance of the input signal is high. This may cause a degradation in gain, linearity and THD. The importance of this effect depends on the desired system performance. There are two restrictions on the analog input signals, VIN+ and VIN-. If the input voltage exceeds the range GND - 0.4V to VDD + 0.3V, the input current must be limited to 10mA because the input protection diodes on the front end of the converter will begin to turn on. In addition, the linearity and the noise performance of the device is ensured only when the differential analog voltage resides within 250mV; however, the FSR input voltage is 320mV.
+5V
+5V VDDO DSP
M 10nF M0 VIN+ VIN- 27 1nF 1nF M1
ADS1203 27 VDD MCLK MDAT GND
0.1F
SPICLK SPISIMO VSSO
Figure 5. Connection Diagram for the ADS1203 Delta-Sigma Modulator Including DSP
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RSW 350(typ) AIN+ 1.5pF CINT 7pF (typ) VCM
High Impedance > 1G
Switching Frequency = CLK 1.5pF RSW 350(typ) AIN-
CINT 7pF (typ) High Impedance > 1G
Figure 6. Input Impedance of the ADS1203 Modulator The ADS1203 can be operated in four modes. Modes 0, 1, and 2 use the internal clock, which is fixed at 20MHz. The modulator can also be operated with an external clock in mode 3. In all modes, the clock is divided by 2 internally and is used as the modulator clock. The frequency of the external clock can vary from 1MHz to 32MHz to adjust for the clock requirements of the application. The modulator topology is fundamentally a 2nd-order, switched-capacitor, delta-sigma modulator, such as the one conceptualized in Figure 7. The analog input voltage and the output of the 1-bit digital-to-analog converter (DAC) are differentiated, providing analog voltages at X2 and X3. The voltages at X2 and X3 are presented to their individual integrators. The output of these integrators progress in a negative or positive direction. When the value of the signal at X4 equals the comparator reference voltage, the output of the comparator switches from negative to positive, or positive to negative, depending on its original state. When the output value of the comparator switches from high to low or vice versa, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage at X6, causing the integrators to progress in the opposite direction. The feedback of the modulator to the front end of the integrators forces the value of the integrator output to track the average of the input.
fCLK X2 X3 X4 DATA VREF Comparator
X(t) fS
Integrator 1
Integrator 2
X6
D/A Converter
Figure 7. Block Diagram of the 2nd-Order Modulator
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DIGITAL OUTPUT
A differential input signal of 0V will ideally produce a stream of ones and zeros that are high 50% of the time and low 50% of the time. A differential input of +256mV will produce a stream of ones and zeros that are high 80% of the time. A differential input of -256mV will produce a stream of ones and zeros that are high 20% of the time. The input voltage versus the output modulator signal is shown in Figure 8.
(each with an implemented filter), the two standard signals (MCLK and MDAT) are provided from the modulator. To reduce the wiring (for example, for galvanic isolation), a single line is preferred. Therefore, in mode 2, the data stream is Manchester encoded.
MODES OF OPERATION
The system clock of the ADS1203 is 20MHz by default. The system clock can be provided either from the internal 20MHz RC oscillator or from an external clock source. For this purpose, the MCLK pin is bidirectional and controlled by the mode setting. The system clock is divided by 2 for the modulator clock. Therefore, the default clock frequency of the modulator is 10MHz. With a possible external clock range of 1MHz to 32MHz, the modulator operates between 500kHz and 16MHz. The four modes of operation for the digital data interface are shown in Table 1.
DIGITAL INTERFACE
INTRODUCTION The analog signal that is connected to the input of the delta-sigma modulator is converted using the clock signal applied to the modulator. The result of the conversion, or modulation, is the output signal DATA from the delta-sigma modulator. In most applications where a direct connection is realized between the delta-sigma modulator and an ASIC, FPGA, DSP, or C
Modulator Output +FS (Analog Input)
-FS (Analog Input) Analog Input
Figure 8. Analog Input vs Modulator Output of the ADS1203 Table 1. Digital Data Interface Modes of Operation
MODE 0 1 2 3 DEFINITION Internal clock, synchronous data output Internal clock, synchronous data output, half output clock frequency Internal clock, Manchester encoded data output External clock, synchronous data output M1 Low Low High High M0 Low High Low High
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Mode 0 In mode 0, the internal RC oscillator is running. The data is provided at the MDAT output pin, and the modulator clock at the MCLK pin. The data is changing at the falling edge of MCLK; therefore, it can safely be strobed with the rising edge. See Figure 1 on page 6. Mode 1 In mode 1, the internal RC oscillator is running. The data is provided at the MDAT output pin. The MCLK pin provides the half modulator clock. The data must be strobed at both the rising and falling edges of MCLK. The data at MDAT is changing in the middle, between the rising and falling edge. In this mode the frequency of both MCLK and MDAT is only 5MHz. See Figure 2 on page 6. Mode 2 In mode 2, the internal RC oscillator is running. The data is Manchester encoded and is provided at the MDAT pin. The MCLK output is set to low. There is no clock output provided in this mode. The Manchester coding allows the data transfer with only a single line. See Figure 3 on page 7. Mode 3 In mode 3, the internal RC oscillator is disabled. The system clock must be provided externally at the input MCLK. The system clock must have twice the frequency of the chosen modulator clock. The data is provided at the MDAT output pin. Since the modulator runs with the half system clock, the data changes at every other falling edge of the external clock. The data can safely be strobed at every other rising edge of MCLK. This mode allows synchronous operation to any digital system or the use of clocks different from 10MHz. See Figure 4 on page 7.
This filter provides the best output performance at the lowest hardware size (for example, count of digital gates). For oversampling ratios in the range of 16 to 256, this is a good choice. All the characterizations in the data sheet are also done using a sinc3 filter with an oversampling ratio of OSR = 256 and an output word width of 16 bits. In a sinc3 filter response (shown in Figure 9 and Figure 10), the location of the first notch occurs at the frequency of output data rate fDATA = fCLK/OSR. The -3dB point is located at half the Nyquist frequency or fDATA/4. For some applications, it may be necessary to use another filter type for better frequency response. This performance can be improved, for example, by a cascaded filter structure. The first decimation stage can be a sinc3 filter with a low OSR and the second stage a high-order filter.
0 -10 -20 Gain (dB) -30 -40 -50 -60 -70 -80 0 200 400 600 800 1000 Frequency (kHz) 1200 1400 1600 OSR = 32 fDATA = 10MHz/32 = 312.5kHz -3dB: 81.9kHz
Figure 9. Frequency Response of Sinc3 Filter
30k
FILTER USAGE
The modulator generates only a bitstream, which does not output a digital word like an analog-to-digital converter (ADC). In order to output a digital word equivalent to the analog input voltage, the bitstream must be processed by a digital filter. A very simple filter built with minimal effort and hardware is the sinc3 filter: H(z) + 1 * z -1 1*z
-OSR 3
25k 20k 15k 10k 5k 0 0
Output Code
OSR = 32 FSR = 32768 ENOB = 9.9 Bits Settling Time = 3 x 1/fDATA = 9.6s
5
10
(2)
15 20 25 30 Number of Output Clocks
35
40
Figure 10. Pulse Response of Sinc3 Filter (fMOD = 10MHz)
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ADS1203
www.ti.com SBAS318 - JUNE 2004
The effective number of bits (ENOB) can be used to compare the performance of ADCs and delta-sigma modulators. Figure 11 shows the ENOB of the ADS1203 with different filter types. In this data sheet, the ENOB is calculated from the SNR: SNR = 1.76dB + 6.02dB x ENOB (3)
data clocks. The data clock is equal to the modulator clock divided by the OSR. For overcurrent protection, filter types other than sinc3 might be a better choice. A simple example is a sinc2 filter. Figure 12 compares the settling time of different filter types. The sincfast is a modified sinc2 filter:
-OSR H(z) + 1 * z -1 1*z 2
1 ) z -2
OSR
(4)
16 14 sincfast 12 ENOB (Bits)
sinc3
10 9 8 sinc2 7 ENOB (Bits) 6 5 4 3 2 1
sinc3
sincfast sinc2
10 8 6 4 2 0 1 10 OSR 100 1000 sinc
sinc
0 0 1 2 3 4 5 6 Settling Time (s) 7 8 9 10
Figure 11. Measured ENOB vs OSR In motor control applications, a very fast response time for overcurrent detection is required. There is a constraint between 1s and 5s with 3 bits to 7 bits resolution. The time for full settling is dependent on the filter order. Therefore, the full settling of the sinc3 filter needs three data clocks and the sinc2 filter needs two
Figure 12. Measured ENOB vs Settling Time For more information, see application note SBAA094, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at www.ti.com.
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ADS1203
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APPLICATIONS
Operating the ADS1203 in a typical application using mode 0 is shown in Figure 13. Measurement of the motor phase current is done via the shunt resistor. For better performance, both signals are filtered. R2 and C2 filter noise on the noninverting input signal, R3 and C3 filter noise on the inverting input signal, and C4 in combination with R2 and R3 filter the differential input signal. In this configuration, the shunt resistor is connected via three wires with the ADS1203. The power supply is taken from the upper gate driver power supply. A decoupling capacitor of 0.1F is recommended for filtering the power supply. If better filtering is required, an additional 1F to 10F capacitor can be added. The control lines M0 and M1 are both low while the part is operating in mode 0. Two output signals, MCLK and MDAT, are connected directly to the optocoupler. The optocoupler can be connected to transfer a direct or inverse signal because the output stage has the capacity to source and sink the same current. The discharge resistor is not needed in parallel with optocoupler diodes because the output driver has push-pull capability to keep the LED diode out of the charge.
The DSP (such as a C28x or C24x) can be directly connected at the output of two channels of the optocoupler. In this configuration, the signals arriving at C28x or C24x are standard delta-sigma modulator signals and are connected directly to the SPICLK and SPISIMO pins. Being a delta-sigma converter, there is no need to have word sync on the serial data, so an SPI is ideal for connection. McBSP would work as well in SPI mode. When component reduction is necessary, the ADS1203 can operate in mode 2, as shown in Figure 14. M1 is high and M0 is low. Only the noninverting input signal is filtered. R2 and C2 filter noise on the input signal. The inverting input is directly connected to the GND pin, which is simultaneously connected to the shunt resistor. The output signal from the ADS1203 is Manchester coded. In this case, only one signal is transmitted. For that reason, one optocoupler channel is used instead of two channels, as in the previous example of Figure 13. Another advantage of this configuration is that the DSP will use only one line per channel instead of two. That permits the use of smaller DSP packages in the application.
HV+
Floating Power Supply
Gated Drive Circuit
R1 C28x or C24x SPICLK
R2 27
D1 5.1V
C1 0.1F
ADS1203 C4 10nF M0 VIN+ VIN- VDD MCLK MDAT
R5 R4
Optocoupler
RSENSE
R3 27
C2 1nF
C3 1nF
SPISIMO GND
M1
Power Supply
Gated Drive Circuit
HV-
Figure 13. Application Diagram in Mode 0
18
ADS1203
www.ti.com SBAS318 - JUNE 2004
HV+
Floating Power Supply
Gated Drive Circuit
R1
R2 27
D1 5.1V
C1 0.1F
ADS1203 M0 VIN+ VDD MCLK MDAT GND
R4 Optocoupler C28x or C24x
RSENSE
Power Supply
C2 0.1F
VIN- M1
Gated Drive Circuit
HV-
Figure 14. Application Diagram in Mode 2
HV+
Floating Power Supply
Gate Drive Circuit
C28x or C24x CVDD ADS1203 C1 0.1F SPICLK SPISIMO
R2 27 + RSENSE - C2 0.1F
M0 VIN+ VIN- M1
VDD MCLK MDAT GND DVDD
Figure 15. Application Diagram without Galvanic Isolation in Mode 0
19
ADS1203
www.ti.com SBAS318 - JUNE 2004
R1 27 + RSENSE -
ADS1203 M0 VIN+ C1 0.1F VIN- M1 VDD MCLK MDAT GND
C4 0.1F
R2 27 + RSENSE -
ADS1203 M0 VIN+ C2 0.1F VIN- M1 VDD MCLK MDAT GND
C5 0.1F
C28x or C24x CVDD R3 27 + RSENSE - ADS1203 M0 VIN+ C3 0.1F VIN- M1 VDD MCLK MDAT GND C6 0.1F
SPICLK SPISIMO SPISIMO SPISIMO DVDD CLK
Figure 16. Application Diagram without Galvanic Isolation in Mode 3
20
ADS1203
www.ti.com SBAS318 - JUNE 2004
LAYOUT CONSIDERATIONS
Power Supplies The ADS1203 requires only one power supply (VDD). If there are separate analog and digital power supplies on the board, a good design approach is to have the ADS1203 connected to the analog power supply. Another possible approach to control noise is the use of a resistor on the power supply. The connection can be made between the ADS1203 power-supply pins via a 10 resistor. The combination of this resistor and the decoupling capacitors between the power-supply pins on the ADS1203 provide some filtering. The analog supply that is used must be well regulated and generate low noise. For designs requiring higher resolution from the ADS1203, power-supply rejection will be a concern. The digital power supply has high-frequency noise that can be capacitively coupled into the analog portion of the ADS1203. This noise can originate from switching power supplies, microprocessors, or DSPs. High-frequency noise will generally be rejected by the external digital filter at integer multiples of MCLK. Just below and above these frequencies, noise will alias back into the passband of the digital filter, affecting the conversion result. Inputs to the ADS1203, such as VIN+, VIN-, and MCLK should not be present before the power supply is on. Violating this condition could cause latch-up. If these signals are present before the supply
is on, series resistors should be used to limit the input current. Experimentation may be the best way to determine the appropriate connection between the ADS1203 and different power supplies. Grounding Analog and digital sections of the design must be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. Do not join the ground planes; instead, connect the two with a moderate signal trace underneath the converter. For multiple converters, connect the two ground planes as close as possible to one central location for all of the converters. In some cases, experimentation may be required to find the best point to connect the two planes together. Decoupling Good decoupling practices must be used for the ADS1203 and for all components in the design. All decoupling capacitors, specifically the 0.1F ceramic capacitors, must be placed as close as possible to the pin being decoupled. A 1F and 10F capacitor, in parallel with the 0.1F ceramic capacitor, can be used to decouple VDD to GND. At least one 0.1F ceramic capacitor must be used to decouple VDD to GND, as well as for the digital supply on each digital component.
21
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2004
PACKAGING INFORMATION
ORDERABLE DEVICE ADS1203IPWR ADS1203IPWT STATUS(1) ACTIVE ACTIVE PACKAGE TYPE TSSOP TSSOP PACKAGE DRAWING PW PW PINS 8 8 PACKAGE QTY 2000 250
(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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